1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for performing process control at an interconnect level on a workpiece.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using the patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used as, for example, a gate electrode structure for transistors. Many times, trench isolation structures are also formed across the substrate of the semiconductor wafer to isolate electrical areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The semiconductor wafer 105 typically includes a plurality of individual semiconductor die 103 arranged in a grid 150. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed across one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on approximately one to four die 103 locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to FIG. 2, a flowchart depiction of a prior art process flow is illustrated. A manufacturing system may process a plurality of semiconductor wafers 105 associated with a batch/lot (block 210). After performing various processes on the semiconductor wafers 105, the manufacturing system may perform a final electrical test on the processed semiconductor wafers 105 (block 220). The final electrical test may comprise measuring a plurality of electrical parameters, such as resistance measurements related to one or more locations on the semiconductor wafers 105. Data from the electrical test may be used by the manufacturing system to determine interconnect characteristics of various contacts and/or vias formed on the semiconductor wafers 105 (block 230).
Upon determining various interconnect characteristics, such as interconnect resistance, and the like, the manufacturing system may calculate adjustments to modify interconnect characteristics for subsequently processed semiconductor wafers 105 by performing adjustments to other processes (block 240). Based upon the calculated adjustments, the system may make adjustments to processing steps performed on subsequent semiconductor wafers 105 (block 250).
Among the problems associated with the current methodology includes the fact that, generally, characterization of interconnect parameters are made after numerous processes are performed on the semiconductor wafers 105. Generally, the interconnect characteristics are only accurately realized after substantial processing of semiconductor wafers 105. Therefore, since the processing of the interconnects is substantially complete with no, or few, process steps remaining, there is an inherent lack of feedback correction abilities based upon the current methodology. Utilizing current processing techniques, controlling interconnect characteristics is difficult and may be inefficient due to the fact that the interconnect characteristics are determined after substantial processing of semiconductor wafers 105. Additionally, there may be a delay between the time period when the interconnect are formed to the time period when a final wafer electrical test is performed, thereby reducing the probability of correcting interconnect errors.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.